1. Field
The present disclosure generally relates to integrated circuits that include optical couplers. More specifically, the present disclosure relates to an integrated circuit that includes an optical coupler which comprises a holographic recording material that diffracts an optical signal out of a plane of the integrated circuit.
2. Related Art
As semiconductor line-widths continue to decrease in size while on-chip clock speeds increase there is a growing the disparity between on-chip communication bandwidth and the off-chip communication bandwidth. This growing disparity is causing off-chip communication bandwidth to become a major bottleneck that limits overall system performance. This problem is especially acute in high-performance computing systems which are based on massively parallel architectures.
Researchers have attempted to use high-speed serial transceivers in chip-to-chip interconnects to improve off-chip communication bandwidth so that it matches the on-chip communication bandwidth. However, the bandwidth-density of high-speed serial transceivers, as well as other existing conductive electrical interconnections, is typically limited by: the topology, contact and parasitic RC limits, and power dissipation when driving low-impedance off-chip signal lines.
Silicon photonics has been proposed as a potential solution for these limitations. Silicon photonics integrates optics and microelectronics monolithically on the same silicon CMOS chip. It relies on silicon waveguide-based modulators with microelectronic control to convert electrical data signals into optical signals propagating in silicon optical waveguides. Because of the large index of refraction, silicon optical waveguides typically have strong light confinement with sub-micrometer-size cross-sectional dimensions. This enables small optical-waveguide bending radii and, therefore, a high density of photonic devices on chip.
However, efficiently coupling light into and out of silicon chips remains a big challenge because of the sub-micrometer mode size of the silicon optical waveguides. Optical fibers, which are one of the conventional transmission media between chips, typically have a mode size of 6-10 μm. The resulting mode-size mismatch can result in significant optical losses. Furthermore, it is anticipated that future high-performance computing systems will use wavelength division multiplexing (WDM) to multiplex multiple data channels onto a single optical fiber in order to meet the desired high bandwidth-density product. In addition, wafer-scale optical testing of the integrated optical devices is important for a low-cost solution.
Several light-coupling techniques have been proposed and implemented. For example, a tapered optical waveguide has been used to couple light into a sub-micron size optical waveguide with low loss. This broadband technique can accommodate a large range of wavelengths, but typically requires edge-coupling of the optical fibers and, thus, usually does not allow a two-dimensional array of optical couplers to be defined on the surface of the chip. As a consequence, a tapered optical waveguide may not allow wafer-scale optical testing of the integrated optical devices. In addition, tapered optical waveguides are often implemented using silicon-on-insulator (SOI) technology with a thick buried-oxide (BOX) layer to the tapered optical-waveguide mode from leaking into the silicon substrate. Such a thick BOX layer may limit the thermal performance of the integrated optical devices. Moreover, precision edge polishing is often required to ensure that the inverse taper tips of a tapered optical waveguide are close to an edge of the chip, which can be difficult to achieve.
Another light-coupling technique uses grating to couple surface-normal or near surface-normal light from optical fibers into sub-micron optical waveguides. These sub-micron grating structures are typically etched onto the optical waveguide directly using high-resolution deep ultraviolet lithography. For optimal performance, the grating structure usually needs to be carefully designed and fabricated. However, even with state-of-the-art CMOS fabrication processes, the center wavelength of such grating couplers usually cannot be accurately controlled. For example, because of substrate scattering and mode mismatch, it is extremely difficult to achieve a coupling loss that is less than 1 dB, especially for chip-to-chip coupling. As a consequence, this coupling technique is usually preferred for a sub-micron SOI platform. It is typically more difficult to design grating couplers for use with a thicker SOI platform, such as one with a 3-μm thick semiconductor layer.
In yet another light-coupling technique, surface-normal couplers are implemented using optical-waveguide tapers and reflecting mirrors. These surface-normal couplers are often used with relatively large silicon optical waveguides, such as those based on a 3-μm thick semiconductor layer in an SOI platform. While reasonable performance has been demonstrated for chip-to-chip coupling using an optical-waveguide taper to convert a 3 μm mode to a 10 μm mode, further performance improvement is very difficult because of: an asymmetric optical-waveguide mode profile, geometry limitations and optical-waveguide taper loss. However, without an optical-waveguide taper, a complicated lens imaging system typically has to be used to minimize the optical loss, which often involves a much more complicated design and fabrication process.
The preceding light-coupling techniques usually require accurate alignment of the components in the integrated optical devices. In particular, for minimal misalignment optical loss, sub-micron alignment tolerance is usually needed. However, the degree of alignment can be difficult to achieve in a low-cost, high-yield design.
Hence, what is needed is an integrated circuit that does not suffer from the above-described problems.